Service Technical Services
FAEs participate at all stages of product development, from specification review to productization. Utilizing our close relationship with semiconductor manufacturers, we propose solutions that combine both hardware and software to provide a complete system solution. We can also project manage as well as provide FAE support for evaluation, verification, quality, and environmental support.
Utilizing our technical information, human network, extensive development and experience, we can respond to various requests such as; ASIC contract design, specification definition, ASIC interface support between customers and manufacturers, and contract design of FPGAs and evaluation boards.
| Specifications I/F | Specification pass development |
|---|---|
| Schematic I/F | Drawing passing development (schematic + test vector) |
| RTL I/F | RTL pass development (RTL description (verified) + testbench) |
| FPGA I/F | FPGA data passing development (RTL or schematic + test vector or testbench) |
| Netlist I/F | Specification pass development (netlist + tester pattern or VCD file) |
Schematic input: Work Veil (PC version)
Simulator ： NC-Verilog,Verilog-XL、ModelSim SE
Debugger ： Verdi
Sign Off Tool : VSO (Toshiba Verilog Sign Off)
Logical Synthesis Tool: Design Compiler
Analysis Tool: Prime Time
FPGA ： ALTERA、XILINX
| Data / Materials | Specifications I/F | Schematic I/F | RTL I/F | Netlist I/F | Remarks |
|---|---|---|---|---|---|
| Feature Overview Block Diagram | ◯ | – | – | – | – |
| Feature description | ◯ | – | – | – | – |
| Simulation specifications | ◯ | – | – | – | Description of operation confirmation items during simulation |
| Logical circuit drawings | – | ◯ | – | – | Logically validated at the gate level |
| Test | – | ◯ | – | ◯ | Test interface language patterns or VCD files |
| RTL source file | – | – | ◯ | – | Verilog-HDL/VHDL format, logical validated |
| Testbench | – | – | ◯ | – | Verilog-HDL/VHDL format, logical validated, verifiable |
| RTLsim output value file | – | – | ◯ | – | Comparison of output values between RTLSim and gate level Sim for logical verification |
| Netlist | – | – | – | ◯ | Verilog-HDL/VHDL format, logical validated |
| Hierarchy tree diagram | – | ◯ | ◯ | – | Hierarchical location of each design data |
| Test settings | – | ◯ | ◯ | ◯ | – |
| Clock information | ◯ | ◯ | ◯ | ◯ | Hierarchical location of each design data |
| Internal/external timing specifications | ◯ | ◯ | ◯ | ◯ | Logic synthesis / for scripting STA |
| External terminal array diagram | ◯ | ◯ | ◯ | ◯ | Buffer type for each terminal is also described. |
| External output terminal load capacity information | ◯ | ◯ | ◯ | ◯ | Used in logical synthesis / real-time operation Sim |
Two types of test data/testbench are required:
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